Devices

10 x 10 bulk-silicon microneedle array, Utah-style, with tips exposed by masking in PDMS before Parylene-C deposition instead of etching. Tip exposure about 50 um, platinum black sites at 33.2 kOhm at 1 kHz, 15 of 16 channels recording in rat with mean spike SNR 12.63. Pei Weihua's group, Institute of Semiconductors, CAS.

Catalog specification sheet - Intracortical

Semi CAS silicon microneedle array with local de-insulation

Record ID
BTSD-ACAD-0103
Reviewed
2026-10-09
Interface
intracortical
Evidence stage
preclinical

Independent, source-linked catalog sheet. Not a manufacturer-issued datasheet, regulatory decision or instructions for clinical use. Human evidence does not establish approval. Source-specific restrictions, conflicts and missing specifications are retained below.

Semi CAS silicon microneedle array with local de-insulation

A 10 x 10 silicon microneedle array for chronic cortical recording from Pei Weihua’s group at the Institute of Semiconductors, Chinese Academy of Sciences, Beijing. The new part is how the tips are opened: the tips are pressed into a thin PDMS mask, Parylene-C is deposited over everything, and pulling the array out of the mask fractures the film at the tip, so no etching is needed. Paper: “A local de-insulation method and its application in neural microneedle array”, Microsystems & Nanoengineering, 2025, DOI 10.1038/s41378-025-00922-6 (PMC12106818, open access). The Institute’s Chinese release of 17 June 2025 gives the same method and a 97% site consistency figure; the paper reports its own non-uniformity numbers, both listed below.

Identity

FieldValue and source scope
DeviceSilicon neural microneedle electrode array chip [1][2]
OriginInstitute of Semiconductors, CAS (Pei Weihua) [1][2]
Funding namedNSFC 62071447; National Key R&D Program 2022YFF1202303 [1]
Regulatory statusResearch device; rat implants only [2]

Geometry and architecture

FieldValue and source scope
Array10 x 10 silicon pillars, maximum 100 channels; a 16-channel (4 x 4) version was implanted [2]
Pillar depth1300 um from a 1800 um double-polished wafer, including fins and corner posts around the array [2]
Tip exposureAcceptable range quoted as 30 to 100 um; four electrodes from one batch averaged 50 +/- 0.77 um [2]
PitchEqual in X and Y, set by the backside pillar pattern; value blank

Materials and fabrication

FieldValue and source scope
SubstrateSilicon pillars etched by ICP from a double-polished wafer, anodically bonded to BF33 glass, annealed under nitrogen so glass fills around the pillars, then polished to expose pillar ends [2]
Backside contactsCr/Au by PVD with lift-off [2]
SingulationFront-side dicing saw cuts the silicon and glass into arrays [2]
InsulationSilane A-174 adhesion layer, Parylene-C about 3 um thick; tips protected by a PDMS mask (10:1, spun at 1250 rpm for 50 s, cured at 80 C for 8 min, about 50 um thick) [2]
Site coatingPlatinum black over Au [2]
PackagingWedge-bonded insulated gold wires to a PCB, wrapped and coated in silicone [2]

Performance envelope

FieldValue and source scope
Site uniformityPaper: tip non-uniformity 3.32 +/- 1.02% across 10 x 10 arrays; range 2.32 +/- 0.57% to 5.22 +/- 1.82% across process settings [2]. Institute release: 97% consistency of exposed sites [1]
Impedance at 1 kHzAu 1.36 MOhm; platinum black 33.2 kOhm [2]
Charge storageAu 0.597 mC/cm2; platinum black 85.7 mC/cm2 at 50 mV/s [2]
AgingIn vitro test equivalent to 32 days in 37 C PBS [2]
In vivoRat, 16-channel array: 15 channels recorded spikes; mean SNR 12.63 +/- 6.64, best channel 28.472 [2]
Process timeThe paper’s comparison lists about 1 h against about 11 h for the etching route [2]

Limits

Rat acute-to-short implants only as reported; no chronic duration was found in the text read. Channel-to-channel SNR spread is large, which the authors tie to implant position and damage. Pitch and needle diameter were not extracted, so they are blank.

References

  1. Institute of Semiconductors, CAS (Chinese), 半导体所植入式脑机接口器件研究取得新进展, 17 June 2025.
  2. A local de-insulation method and its application in neural microneedle array, Microsystems & Nanoengineering (2025), DOI 10.1038/s41378-025-00922-6; full text via Europe PMC PMC12106818.